1 ? fn2963.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1997, 2007, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. hs-3182 arinc 429 bus interf ace line driver circuit the hs-3182 is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of arinc 429. this device is intended to be used with a companion chip, hs-3282 cmos arinc bus interface circuit, which provides the data formatting and processor interface function. all logic inputs are ttl and cmos compatible. in addition to the data (a) and data (b) inputs, there are also inputs for clock and sync signals which are and?d with the data inputs. this feature enhan ces system performance and allows the hs-3182 to be used with devices other than the hs-3182. three power supplies are necessa ry to operate the hs-3182: +v = +15v 10%, -v = -15v 10%, and v1 = 5v 5%. v ref is used to program the differential output voltage swing such that v out (diff) = 2vref. typically, v ref = v1 = 5v 5%, but a separate power supply may be used for vref which should not exceed 6v. the driver output impedance is 75 20% at +25c. driver output rise and fall times are independently programmed through the use of two external capacitors connected to the ca and cb inputs. typical capacitor values are ca = cb = 75pf for high-speed operation (100kbps), and ca = cb = 300pf for low-speed operation (12kbps to 14.5kbps). the outputs are protected against overvoltage and short circuit as shown in the block diagram. the hs-3182 is designed to operate over an ambient temperature range of -55c to +125c, or -40c to +85c. features ? rohs/pb-free available for sbdip package (100% gold termination finish) ? ttl and cmos compatible inputs ? adjustable rise and fall times via two external capacitors ? programmable output differential voltage via v ref input ? operates at data rates up to 100k bits/s ? output short circuit proof and contains overvoltage protection ? outputs are inhibited (0v) if data (a) and data (b) inputs are both in the ?logic one? state ? data (a) and data (b) signals are ?and?d? with clock and sync signals ? full military temperature range pinouts hs-3182 (16 ld sbdip) top view hs-3182 (28 ld clcc) top view table 1. truth table sync clk data (a) data (b) a out b out comments xl x x 0v 0v null lx x x 0v 0v null hh l l 0v 0v null hh l h -v ref +v ref low hh h l +v ref -v ref high hh h h 0v 0v null 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v ref gnd sync data (a) c a a out gnd -v v 1 clk data (b) c b b out nc +v nc 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 nc data (a) nc nc ca nc nc clk nc data (b) cb nc nc nc nc aout -v gnd +v nc bout sync gnd nc vref v1 nc nc data sheet may 30, 2008
2 fn2963.3 may 30, 2008 block diagram ordering information part number ordering number part marking temp. range (c) package pkg. dwg. # hs1-3182-8 5962-8687901ea hs1-3182-8 rd -55 to +125 16 ld sbdip, solder seal (pb-free) d16.3 hs1-3182-9+ hs1-3182-9+ hs1-3182-9+ rd -40 to +85 16 ld sbdip, solder seal (pb-free) d16.3 HS4-3182-8 5962-86879013a hs4- 3182-8 rd -55 to +125 28 ld ter clcc, solder seal j28.a note: these intersil pb-free hermetic pack aged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. level shifter and slope control (a) level shifter and slope control (b) current regulator data (a) clock vref sync data (b) v1 (4) (14) (1) (3) (13) (16) (2) (9) (5) +v ca output driver (a) rout/2 rout/2 output driver (b) gnd (8) -v cb (7) (12) over-voltage protection f a fb cl aout bout rl (6) (11) hs-3182 arinc driver circuit 16 lead dip gnd gnd -v data (b) data (a) sync clock v1 vref c a c b +v aout bout to bus (see note) pin number 10, 15 = nc -15v (7) (8) (2) (9) +15v ca cb (12) (5) +5v (1) (16) (14) (3) pin numbers indicated by ( ) hs-3282 cmos arinc circuit 429d0 429d0 31 32 (4) (13) typical application note: the rise and fall time of the output s are set to arinc specified values by c a and c b . typical c a = c b = 75pf for high speed and 300pf for low speed operation. the output hi and low leve ls are set to arinc specifications by v ref . hs-3182
3 fn2963.3 may 30, 2008 absolute maximum rati ngs thermal information voltage between +v and -v terminals . . . . . . . . . . . . . . . . . . . .40v v1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6v logic input voltage . . . . . . . . . . . . . . . . . . . gnd -0.3v to v1 +0.3v output short circuit duration. . . . . . . . . . . . . . . . . . . . . . . . (note 3) output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . (note 4) operating conditions operating voltage +v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v 10% -v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15v 10% v1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% vref (for arinc 429) . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% operating temperature range hs-3182-9+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c hs-3182-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c thermal resistance (typical) ja (c/w) jc (c/w) sbdip package . . . . . . . . . . . . . . . . . . 68 12 clcc package . . . . . . . . . . . . . . . . . . 54 10 storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +175c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp die characteristics number of transistors or gates . . . . . . . . . . . . . . . . . . . . . . . . . 133 caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. 2. jc , the ?case temp? location is the center of the package underside. 3. heat sink may be required for 100k bits/s at +125c and output short circuit at +125c. 4. the fuses used for output overvoltage protection may be blown by a fault at each output of greater than 6.5v relative to gnd . dc electrical specifications parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establis hed by characterization and are not production tested. dc parameter symbol conditions (note 5) min max units supply current +v (operating) i ccop (+v) no load (0k to 100k bits/s) - 16 ma supply current -v (operating) i ccop (-v) no load (0k to 100k bits/s) -16 - ma supply current v 1 (operating) i ccop (v 1 ) no load (0k to 100k bits/s) - 975 a supply current v ref (operating) i ccop (v ref ) no load (0k to 100k bits/s) -1.0 - ma logic ?1? input voltage v ih 2.0 - v logic ?0? input voltage v il -0.5v output voltage high (output to gnd) v oh no load (0k to 100k bits/s) v ref (-250mv) v ref (+250mv) output voltage low (output to gnd) v ol no load (0k to 100k bits/s) -v ref (-250mv) -v ref (+250mv) output voltage null v null no load (0k to 100k bits/s) -250 +250 mv input current (input low) i il -20 - ma input current (input high) i ih -10ma output short circuit current (output high) i ohsc short to gnd - -80 ma output short circuit current (output low) i olsc short to gnd 80 - ma output impedance z o t a = +25c 60 90 notes: 5. +v = +15v 10%, -v = -15v 10%, v 1 = v ref = 5v 5%, unless otherwise specified t a = -40c to +85c for hs-3182-9+ and t a = -55c to +125c for hs-3182-8. hs-3182
4 fn2963.3 may 30, 2008 ac electrical specifications ac parameter symbol conditions (note 6) min max units rise time (a out , b out )t r c a = c b = 75pf, (note 7) 1 2 s (at t a = -55c only) 0.9 2.4 s c a = c b = 300pf, (note 7) 3 9 s fall time (a out , b out )t f c a = c b = 75pf, (note 8) 1 2 s (at t a = -55c only) 0.9 2.4 s c a = c b = 300pf, (note 8) 3 9 s propagation delay input to output t plh c a = c b = 75pf, no load - 3.3 s propagation delay input to output t phl c a = c b = 75pf, no load - 3.3 s notes: 6. +v = +15v, -v = -15v, v 1 = v ref = 5v, unless otherwise specified t a = -40c to +85c for hs-3182-9+ and t a = -55c to +125c for hs-3182-8. 7. t r measured 50% to 90% x 2, no load. 8. t f measured 50% to 10% x 2, no load. electrical specifications parameter symbol conditions (note 9) min max units input capacitance c in t a = +25c - 15 pf supply current +v (short circuit) i sc (+v) short to gnd, t a = +25c - 150 ma supply current -v (short circuit) i sc (-v) short to gnd, t a = +25c -150 - ma notes: 9. limits established by characteri zation and are not production tested. power specifications nominal power at +25c, +v = +15v, -v = -15v, v1 = vref = 5v, notes 10, 12 data rate (k bits/s) load +v v- v 1 chip power power dissipation in load 0 to 100 no load 11ma -10ma 600a 325mw 0 12.5 to 14 full load, note 11 24ma -24ma 600a 660mw 60mw 100 full load, note 11 46ma -46ma 600a 1 watt 325mw notes: 10. heat sink may be required for 100k bits/s at +125c and output short circuit at +125c. thermal characteristics: t (case) = t (junction) - (junction - case) p (dissipation) . where: t (junction max) = +175c (junction - case) = 10.9c/w (6.1c/w for lcc) (junction - ambient) = 73.5c/w (54.0c/w for lcc) 11. full load for arinc 429: r l = 400 and c l = 30,000pf in parallel between a out and b out (see ?block diagram? on page 2). 12. output overvoltage protection: the fuses used for output overvo ltage protection may be blown by a fault at each output of gre ater than 6.5v relative to gnd. hs-3182
5 fn2963.3 may 30, 2008 driver waveforms notes: t r measured 50% to 90% x 2 t f measured 50% to 10% x 2 v ih = 5v v ol = -4.75v to -5.25v v il = 0v v oh = 4.75v to 5.25v when the data (a) input is in the logic one state and the data (b) input is in the logic zero state, a out is equal to v ref and b out is equal to -v ref . this constitutes the output high state. data (a) and data (b) both in the logic zero state causes both a out and b out to be equal to 0v which designates the output null state. data (a) in the logic zero state and data (b) in the logic one state causes a out to be equal to -v ref and b out to be equal to v ref which is the output low state. burn-in schematic notes: r = 400 5% c 1 = 0.03mf 20% c 2 = c 3 = 500pf, npo +v = +15.5v 0.5v -v = -15.5v 0.5v v 1 = +5.5v 0.5v a 0.0mf decoupling capacitor is required on each of the three supply lines (+v, -v and v 1 ) at every 3rd burn-in socket. ambient temp. max. = +125c. package = 16 lead side brazed dip. pulse conditions = a & b = 6.25khz 10%. b is delayed one-half cycle and in sync with a. v ih = 2.0v min. v il = 0.5v max. data (a) 0v data (b) 0v v ref a out 0v b out 0v t phl -v ref a out - b out 0v differential output 50% 50% 50% 50% t plh t r t f 2v ref -v ref v ref high null low -2v ref adj. by c b adj. by c a 5v 0v 5v 0v +4.75v to +5.25v -4.75v to -5.25v +4.75v to +5.25v -4.75v to -5.25v +9.5v to +10.5v note: outputs unloaded -9.5v to -10.5v v 1 data (b) +v c 1 gnd -v data (a) 16 15 14 13 12 11 10 9 12345678 c 3 c 2 r hs-3182 v il v ih v ih v il a b hs-3182
6 fn2963.3 may 30, 2008 hs-3182 ceramic leadless chip carrier packages (clcc) d j x 45 o d3 b h x 45 o a a1 e l l3 e b3 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 0.010 e h s s 0.010 e f s s -e- 0.007 e f m s hs b1 -h- -f- j28.a mil-std-1835 cqcc1-n28 (c-4) 28 pad ceramic leadless chip carrier package symbol inches millimeters notes min max min max a 0.060 0.100 1.52 2.54 6, 7 a1 0.050 0.088 1.27 2.23 - b----- b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.442 0.460 11.23 11.68 - d1 0.300 bsc 7.62 bsc - d2 0.150 bsc 3.81 bsc - d3 - 0.460 - 11.68 2 e 0.442 0.460 11.23 11.68 - e1 0.300 bsc 7.62 bsc - e2 0.150 bsc 3.81 bsc - e3 - 0.460 - 11.68 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.90 2.41 - l3 0.003 0.015 0.08 0.038 - nd 7 7 3 ne 7 7 3 n28 283 rev. 0 5/18/94 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the opti onal plane 2 terminals. 2. unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained bet ween all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol ?n? is the maximum number of terminals. symbols ?nd? and ?ne? are the number of terminals along the sides of length ?d? and ?e?, respectively. 4. the required plane 1 terminals an d optional plane 2 terminals (if used) shall be elec trically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturer?s option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. dimension ?a? controls the over all package thickness. the maxi- mum ?a? dimension is package he ight before being solder dipped. 8. dimensioning and tolerancing per ansi y14.5m-1982. 9. controlling dimension: inch.
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2963.3 may 30, 2008 hs-3182 ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n16 168 rev. 0 4/94
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